S912XHZ512F1VAG Datasheet, PDF (442/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 11 Motor Controller (MC10B12CV2) Block Description
11.4 Functional Description
11.4.1 Modes of Operation
11.4.1.1 PWM Output Modes
The motor controller is configurable between three output modes.
• Dual full H-bridge mode can be used to control either a stepper motor or a 360° air core instrument.
In this case two PWM channels are combined.
• In full H-bridge mode, each PWM channel is updated independently.
• In half H-bridge mode, one pin of the PWM channel can generate a PWM signal to control a 90°
air core instrument (or other load requiring a PWM signal) and the other pin is unused.
The mode of operation for each PWM channel is determined by the corresponding MCOM[1:0] bits in
channel control registers. After a reset occurs, each PWM channel will be disabled, the corresponding pins
are released.
Each PWM channel consists of two pins. One output pin will generate a PWM signal. The other will
operate as logic high or low output depending on the state of the RECIRC bit (refer to Section 11.4.1.3.3,
“RECIRC Bit”), while in (dual) full H-bridge mode, or will be released, while in half H-bridge mode. The
state of the S bit in the duty cycle register determines the pin where the PWM signal is driven in full
H-bridge mode. While in half H-bridge mode, the state of the released pin is determined by other modules
associated with this pin.
Associated with each PWM channel pair n are two PWM channels, x and x + 1, where x = 2 * n and n
(0,1,2... 5) is the PWM channel pair number. Duty cycle register x controls the sign of the PWM signal
(which pin drives the PWM signal) and the duty cycle of the PWM signal for motor controller channel x.
The pins associated with PWM channel x are MnC0P and MnC0M. Similarly, duty cycle register x + 1
controls the sign of the PWM signal and the duty cycle of the PWM signal for channel x + 1. The pins
associated with PWM channel x + 1 are MnC1P and MnC1M. This is summarized in Table 11-11.
Table 11-11. Corresponding Registers and Pin Names for each PWM Channel Pair
PWM Channel
Pair Number
PWM
Channel
Control
Register
Duty Cycle Register
Channel Number
Pin
Names
MCMCx
n
MCMCx+1
MCDCx
MCDCx+1
PWM Channel x, x = 2⋅n
PWM Channel x+1, x = 2⋅n
MnC0M
MnC0P
MnC1M
MnC1P
MCMC0
0
MCMC1
MCDC0
MCDC1
PWM Channel 0
PWM Channel 1
M0C0M
M0C0P
M0C1M
M0C1P
MC9S12XHZ512 Data Sheet, Rev. 1.06
442
Freescale Semiconductor