S912XHZ512F1VAG Datasheet, PDF (446/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 11 Motor Controller (MC10B12CV2) Block Description
Motor Controller
Timer Counter
Clock
Motor Controller
Timer Counter
0
PWM Output
15
1 Period
100 Counts
99 0
15
1 Period
100 Counts
99 0
DITH = 0, MCAM[1:0] = 01, MCDCx = 15, MCPER = 100, RECIRC = 0
Right aligned (MCAM[1:0] = 10): The output will start inactive (high if RECIRC = 0 and low if
RECIRC = 1) and will turn active after the number of counts specified by the difference of the contents of
period register and the corresponding duty cycle register.
Motor Controller
Timer Counter
Clock
Motor Controller
Timer Counter
0
85
99 0
85
99 0
PWM Output
1 Period
100 Counts
1 Period
100 Counts
DITH = 0, MCAM[1:0] = 10, MCDCx = 15, MCPER = 100, RECIRC = 0
Center aligned (MCAM[1:0] = 11): Even periods will be output left aligned, odd periods will be output
right aligned. PWM operation starts with the even period after the channel has been enabled. PWM
operation in center aligned mode might start with the odd period if the channel has not been disabled before
changing the alignment mode to center aligned.
Motor Controller
Timer Counter
Clock
Motor Controller
Timer Counter
0
15
99 0
85
99 0
PWM Output
1 Period
100 Counts
1 Period
100 Counts
DITH = 0, MCAM[1:0] = 11, MCDCx = 15, MCPER = 100, RECIRC = 0
MC9S12XHZ512 Data Sheet, Rev. 1.06
446
Freescale Semiconductor