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S912XHZ512F1VAG Datasheet, PDF (922/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256 | |||
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Appendix A Electrical Characteristics
In Table A-23 the timing characteristics for master mode are listed.
Table A-23. SPI Master Mode Timing Characteristics
Num
1
1
2
3
4
5
6
9
10
11
12
13
C
Characteristic
D SCK frequency
D SCK period
D Enable lead time
D Enable lag time
D Clock (SCK) high or low time
D Data setup time (inputs)
D Data hold time (inputs)
D Data valid after SCK edge
D Data valid after SS fall (CPHA = 0)
D Data hold time (outputs)
D Rise and fall time inputs
D Rise and fall time outputs
Symbol
Min
Typ
fsck
1/2048
â
tsck
2
â
tlead
â
1/2
tlag
â
1/2
twsck
â
1/2
tsu
8
â
thi
8
â
tvsck
â
â
tvss
â
â
tho
20
â
trï¬
â
â
trfo
â
â
Max
1/2
2048
â
â
â
â
â
29
15
â
8
8
Unit
fbus
tbus
tsck
tsck
tsck
ns
ns
ns
ns
ns
ns
ns
A.8.2 Slave Mode
In Figure A-8 the timing diagram for slave mode with transmission format CPHA = 0 is depicted.
SS
(Input)
SCK
(CPOL = 0)
(Input)
SCK
(CPOL = 1)
(Input) 10
7
MISO
(Output)
2
See
Note
1
12
4
4
12
Slave MSB
9
Bit 6 . . . 1
13 3
13
11
11
Slave LSB OUT
MOSI
(Input)
5
6
MSB IN
Bit 6 . . . 1
LSB IN
NOTE: Not deï¬ned
Figure A-8. SPI Slave Timing (CPHA = 0)
8
See
Note
MC9S12XHZ512 Data Sheet, Rev. 1.06
922
Freescale Semiconductor
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