S912XHZ512F1VAG Datasheet, PDF (49/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 1 MC9S12XHZ Family Device Overview
Table 1-7. Chip Modes and Data Sources
Chip Modes
BKGD =
MODC
PE6 =
MODB
PE5 =
MODA
PK7 =
ROMCTL
PE3 =
EROMCTL
Data Source¹
Normal single chip
1
0
0
X
X
Internal
Special single chip
0
0
0
Emulation single chip
0
0
1
X
0
Emulation memory
X
1
Internal Flash
Normal expanded
1
0
1
0
X
External application
1
X
Internal Flash
Emulation expanded
0
1
1
0
X
External application
1
0
Emulation memory
1
1
Internal Flash
Special test
0
1
0
0
X
External application
1
X
Internal Flash
1 _{Internal means resources inside the MCU are read/written.}
Internal Flash means Flash resources inside the MCU are read/written.
Emulation memory means resources inside the emulator are read/written (PRU registers, Flash replacement, RAM, EEPROM,
and register space are always considered internal).
External application means resources residing outside the MCU are read/written.
The configuration of the oscillator can be selected using the XCLKS signal (see Table 1-8). For a detailed
description please refer to the CRG block description chapter.
Table 1-8. Clock Selection Based on PE7
PE7 = XCLKS
Description
0
Loop controlled Pierce oscillator selected
1
Full swing Pierce oscillator or external clock source selected
1.5 Modes of Operation
1.5.1 User Modes
1.5.1.1 Normal Expanded Mode
Ports K, A, and B are configured as a 23-bit address bus, ports C and D are configured as a 16-bit data bus,
and port E provides bus control and status signals. This mode allows 16-bit external memory and
peripheral devices to be interfaced to the system. The fastest external bus rate is divide by 2 from the
internal bus rate.
1.5.1.2 Normal Single-Chip Mode
There is no external bus in this mode. The processor program is executed from internal memory. Ports A,
B,C,D, K, and most pins of port E are available as general-purpose I/O.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
49