S912XHZ512F1VAG Datasheet, PDF (634/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 17 Periodic Interrupt Timer (S12PIT24B4CV1)
17.3.0.8 PIT Load Register 0 to 3 (PITLD0–3)
Module Base + 0x0008, 0x0009
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
W
Reset 0
0
0
0
0
0
0000000000
Figure 17-11. PIT Load Register 0 (PITLD0)
Module Base + 0x000C, 0x000D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
W
Reset 0
0
0
0
0
0
0000000000
Figure 17-12. PIT Load Register 1 (PITLD1)
Module Base + 0x0010, 0x0011
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
W
Reset 0
0
0
0
0
0
0000000000
Figure 17-13. PIT Load Register 2 (PITLD2)
Module Base + 0x0014, 0x0015
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
W
Reset 0
0
0
0
0
0
0000000000
Figure 17-14. PIT Load Register 3 (PITLD3)
Read: Anytime
Write: Anytime
Table 17-8. PITLD0–3 Field Descriptions
Field
Description
15:0
PLD[15:0]
PIT Load Bits 15:0 — These bits set the 16-bit modulus down-counter load value. Writing a new value into the
PITLD register must be a 16-bit access, to ensure data consistency. It will not restart the timer. When the timer
has counted down to zero the PTF time-out flag will be set and the register value will be loaded. The PFLT bits
in the PITFLT register can be used to immediately update the count register with the new value if an immediate
load is desired.
MC9S12XHZ512 Data Sheet, Rev. 1.06
634
Freescale Semiconductor