S912XHZ512F1VAG Datasheet, PDF (860/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 25 Memory Mapping Control (S12XMMCV3)
25.3.2.4 Direct Page Register (DIRECT)
Address: 0x0011
R
W
Reset
7
DP15
0
6
DP14
0
5
DP13
0
4
DP12
0
3
DP11
0
2
DP10
0
1
DP9
0
0
DP8
0
Figure 25-8. Direct Register (DIRECT)
Read: Anytime
Write: anytime in special modes, one time only in other modes.
This register determines the position of the 256 Byte direct page within the memory map.It is valid for both
global and local mapping scheme.
Table 25-9. DIRECT Field Descriptions
Field
7–0
DP[15:8]
Description
Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct
addressing mode. The bits from this register form bits [15:8] of the address (see Figure 25-9).
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Global Address [22:0]
Bit22
Bit16 Bit15
Bit8 Bit7
Bit0
DP [15:8]
CPU Address [15:0]
Figure 25-9. DIRECT Address Mapping
Bits [22:16] of the global address will be formed by the GPAGE[6:0] bits in case the CPU executes a global
instruction in direct addressing mode or by the appropriate local address to the global address expansion
(refer to Section 25.4.2.1.1, “Expansion of the Local Address Map).
Example 25-2. This example demonstrates usage of the Direct Addressing Mode
MOVB
#0x80,DIRECT
;Set DIRECT register to 0x80. Write once only.
;Global data accesses to the range 0xXX_80XX can be direct.
;Logical data accesses to the range 0x80XX are direct.
LDY
<00
;Load the Y index register from 0x8000 (direct access).
;< operator forces direct access on some assemblers but in
;many cases assemblers are “direct page aware” and can
MC9S12XHZ512 Data Sheet, Rev. 1.06
860
Freescale Semiconductor