S912XHZ512F1VAG Datasheet, PDF (787/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 22 S12X Debug (S12XDBGV3) Module
22.4.1 S12XDBG Operation
Arming the S12XDBG module by setting ARM in DBGC1 allows triggering, and storing of data in the
trace buffer and can be used to cause breakpoints to the CPU12X or the XGATE module. The DBG module
is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer.
The comparators monitor the bus activity of the CPU12X and XGATE. Comparators can be configured to
monitor address and databus. Comparators can also be configured to mask out individual data bus bits
during a compare and to use R/W and word/byte access qualification in the comparison. When a match
with a comparator register value occurs the associated control logic can trigger the state sequencer to
another state (see Figure 22-22). Either forced or tagged triggers are possible. Using a forced trigger, the
trigger is generated immediately on a comparator match. Using a tagged trigger, at a comparator match,
the instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction
queue is a trigger generated. In the case of a transition to Final State, bus tracing is triggered and/or a
breakpoint can be generated. Tracing of both CPU12X and/or XGATE bus activity is possible.
Independent of the state sequencer, a breakpoint can be triggered by the external TAGHI / TAGLO signals
or by an XGATE S/W breakpoint request or by writing to the TRIG bit in the DBGC1 control register.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads.
22.4.2 Comparator Modes
The S12XDBG contains four comparators, A, B, C, and D. Each comparator can be configured to monitor
CPU12X or XGATE buses. Each comparator compares the selected address bus with the address stored in
DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparators A and C also compare the data buses
to the data stored in DBGXDH, DBGXDL and allow masking of individual data bus bits.
S12X comparator matches are disabled in BDM and during BDM accesses.
The comparator match control logic configures comparators to monitor the buses for an exact address or
an address range. The comparator configuration is controlled by the control register contents and the range
control by the DBGC2 contents.
On a match a trigger can initiate a transition to another state sequencer state (see Section 22.4.3”). The
comparator control register also allows the type of access to be included in the comparison through the use
of the RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled
for the associated comparator and the RW bit selects either a read or write access for a valid match.
Similarly the SZE and SZ bits allows the size of access (word or byte) to be considered in the compare.
Only comparators B and D feature SZE and SZ.
The TAG bit in each comparator control register is used to determine the triggering condition. By setting
TAG, the comparator will qualify a match with the output of opcode tracking logic and a trigger occurs
before the tagged instruction executes (tagged-type trigger). Whilst tagging, the RW, RWE, SZE, and SZ
bits are ignored and the comparator register must be loaded with the exact opcode address.
If the TAG bit is clear (forced type trigger) a comparator match is generated when the selected address
appears on the system address bus. If the selected address is an opcode address, the match is generated
MC9S12XHZ512 Data Sheet Rev. 1.06
Freescale Semiconductor
787