S912XHZ512F1VAG Datasheet, PDF (104/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.10.4 Port S Reduced Drive Register (RDRS)
Module Base + 0x000B
R
W
Reset
7
RDRS7
0
6
RDRS6
5
RDRS5
4
RDRS4
3
RDRS3
2
RDRS2
0
0
0
0
0
Figure 2-53. Port S Reduced Drive Register (RDRS)
1
RDRS1
0
0
RDRS0
0
Read: Anytime. Write: Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 2-39. RDRS Field Descriptions
Field
Description
7:0
Reduced Drive Port S
RDRS[7:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
2.3.10.5 Port S Pull Device Enable Register (PERS)
Module Base + 0x000C
7
R
PERS7
W
6
PERS6
5
PERS5
4
PERS4
3
PERS3
2
PERS2
1
PERS1
0
PERS0
Reset
0
0
0
0
0
0
0
0
Figure 2-54. Port S Pull Device Enable Register (PERS)
Read: Anytime. Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated on configured input or
wired-or (open drain) output pins. If a pin is configured as push-pull output, the corresponding Pull Device
Enable Register bit has no effect.
Table 2-40. PERS Field Descriptions
Field
7:0
Pull Device Enable Port S
PERS[7:0] 0 Pull-up or pull-down device is disabled.
1 Pull-up or pull-down device is enabled.
Description
MC9S12XHZ512 Data Sheet, Rev. 1.06
104
Freescale Semiconductor