S912XHZ512F1VAG Datasheet, PDF(771/978 Page) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

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S912XHZ512F1VAG Datasheet, PDF (771/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

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Chapter 22 S12X Debug (S12XDBGV3) Module

Table 22-5. DBGC1 Field Descriptions (continued)

Field

5

XGSBPE

4

BDM

3â2

DBGBRK

1â0

COMRV

Description

XGATE S/W Breakpoint Enable â The XGSBPE bit controls whether an XGATE S/W breakpoint request is

passed to the CPU12X. The XGATE S/W breakpoint request is handled by the S12XDBG module, which can

request an CPU12X breakpoint depending on the state of this bit.

0 XGATE S/W breakpoint request is disabled

1 XGATE S/W breakpoint request is enabled

Background Debug Mode Enable â This bit determines if an S12X breakpoint causes the system to enter

Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled

by the ENBDM bit in the BDM module, then breakpoints default to SWI.

0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.

1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI

S12XDBG Breakpoint Enable Bits â The DBGBRK bits control whether the debugger will request a breakpoint

to either CPU12X or XGATE or both upon reaching the state sequencer Final State. If tracing is enabled, the

breakpoint is generated on completion of the tracing session. If tracing is not enabled, the breakpoint is

generated immediately. Please refer to Section 22.4.7 for further details. XGATE software breakpoints are

independent of the DBGBRK bits. XGATE software breakpoints force a breakpoint to the CPU12X independent

of the DBGBRK bit ï¬eld conï¬guration. See Table 22-6.

Comparator Register Visibility Bits â These bits determine which bank of comparator register is visible in the

8-byte window of the S12XDBG module address map, located between 0x0028 to 0x002F. Furthermore these

bits determine which register is visible at the address 0x0027. See Table 22-7.

DBGBRK

00

01

10

11

Table 22-6. DBGBRK Encoding

Resource Halted by Breakpoint

No breakpoint generated

XGATE breakpoint generated

CPU12X breakpoint generated

Breakpoints generated for CPU12X and XGATE

COMRV

00

01

10

11

Table 22-7. COMRV Encoding

Visible Comparator

Comparator A

Comparator B

Comparator C

Comparator D

Visible Register at 0x0027

DBGSCR1

DBGSCR2

DBGSCR3

DBGMFR

MC9S12XHZ512 Data Sheet Rev. 1.06

Freescale Semiconductor

771

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