S912XHZ512F1VAG Datasheet, PDF (24/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 1 MC9S12XHZ Family Device Overview
• On-Chip Voltage Regulator
— Two parallel, linear voltage regulators with bandgap reference
— Low-voltage detect (LVD) with low-voltage interrupt (LVI)
— Power-on reset (POR) circuit
— 3.3-V–5.5-V operation
— Low-voltage reset (LVR)
— Ultra low-power wake-up timer
• 144-pin LQFP and 112-pin LQFP packages
— I/O lines with 5-V input and drive capability
— Input threshold on external bus interface inputs switchable for 3.3-V or 5-V operation
— 5-V A/D converter inputs
— 8 key wake up interrupts with digital filtering and programmable rising/falling edge trigger
• Operation at 80 MHz equivalent to 40-MHz bus speed
• Development support
— Single-wire background debug™ mode (BDM)
— Four on-chip hardware breakpoints
1.1.2 Modes of Operation
User modes:
• Normal and emulation operating modes
— Normal single-chip mode
— Normal expanded mode
— Emulation of single-chip mode
— Emulation of expanded mode
• Special Operating Modes
— Special single-chip mode with active background debug mode
— Special test mode (Freescale use only)
Low-power modes:
• System stop modes
— Pseudo stop mode
— Full stop mode
• System wait mode
1.1.3 Block Diagram
Figure 1-1 shows a block diagram of the MC912XHZ family.
MC9S12XHZ512 Data Sheet, Rev. 1.06
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Freescale Semiconductor