S912XHZ512F1VAG Datasheet, PDF (26/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 1 MC9S12XHZ Family Device Overview
1.1.4 Device Memory Map
Table 1-1 shows the device memory map for the MC912XHZ family.
Unimplemented register space shown in Table 1-1 is not allocated to any module. Writing to these
locations have no effect. Read access to these locations returns zero.
Table 1-1. Device Register Memory Map
Address
Offset
0x0000–0x0009
0x000A–0x000B
0x000C–0x000D
0x000E–0x000F
0x0010–0x0017
0x0018–0x0019
0x001A–0x001B
0x001C–0x001F
0x0020–0x002F
0x0030–0x0031
0x0032–0x0033
0x0034–0x003F
0x0040–0x007F
0x0080–0x00AF
0x00B0–0x00BF
0x00C0–0x00C7
0x00C8–0x00CF
0x00D0–0x00D7
0x00D8–0x00DF
0x00E0–0x00FF
0x0100–0x010F
0x0110–0x011B
0x011C–0x011F
0x0120–0x0137
0x0138–0x013F
0x0140–0x017F
0x0180–0x01BF
0x01C0–0x01FF
0x0200–0x027F
0x0280–0x0287
0x0288–0x028F
0x0290–0x0297
0x0298–0x029F
Module
PIM (port integration module)
MMC (memory map control)
PIM (port integration module)
EBI (external bus interface)
MMC (memory map control)
Unimplemented
Device ID register
PIM (port integration module)
DBG (debug module)
MMC (memory map control)
PIM (port integration module)
CRG (clock and reset generator)
ECT (enhanced capture timer 16-bit 8-channel)
ATD (analog-to-digital converter 10-bit 16-channel)
INT (interrupt module)
IIC0 (inter IC bus)
SCI0 (serial communications interface)
SCI1 (serial communications interface)
SPI (serial peripheral interface)
Unimplemented
Flash control registers
EEPROM control registers
MMC (memory map control)
Liquid Crystal Display Driver 32x4 (LCD)
IIC1 (inter IC bus)
CAN0 (scalable CAN)
CAN1 (scalable CAN)
MC (motor controller)
PIM (port integration module)
SSD4 (stepper stall detector)
SSD0 (stepper stall detector)
SSD1 (stepper stall detector)
SSD2 (stepper stall detector)
Size
(Bytes)
10
2
2
2
8
2
2
4
16
2
2
12
64
48
16
8
8
8
8
32
16
12
4
24
8
64
64
64
128
8
8
8
8
MC9S12XHZ512 Data Sheet, Rev. 1.06
26
Freescale Semiconductor