S912XHZ512F1VAG Datasheet, PDF (692/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Module Base + 0x0019
R
W
Reset
7
Bit 7
0
6
Bit 6
0
5
Bit 5
0
4
Bit 4
0
3
Bit 3
0
2
Bit 2
0
1
Bit 1
0
0
Bit 0
0
Figure 19-29. Timer Input Capture/Output Compare Register 4 Low (TC4)
Module Base + 0x001A
R
W
Reset
15
Bit 15
0
14
Bit 14
0
13
Bit 13
0
12
Bit 12
0
11
Bit 11
0
10
Bit 10
0
9
Bit 9
0
8
Bit 8
0
Figure 19-30. Timer Input Capture/Output Compare Register 5 High (TC5)
Module Base + 0x001B
R
W
Reset
7
Bit 7
0
6
Bit 6
0
5
Bit 5
0
4
Bit 4
0
3
Bit 3
0
2
Bit 2
0
1
Bit 1
0
0
Bit 0
0
Figure 19-31. Timer Input Capture/Output Compare Register 5 Low (TC5)
Module Base + 0x001C
R
W
Reset
15
Bit 15
0
14
Bit 14
0
13
Bit 13
0
12
Bit 12
0
11
Bit 11
0
10
Bit 10
0
9
Bit 9
0
8
Bit 8
0
Figure 19-32. Timer Input Capture/Output Compare Register 6 High (TC6)
Module Base + 0x001D
R
W
Reset
7
Bit 7
0
6
Bit 6
0
5
Bit 5
0
4
Bit 4
0
3
Bit 3
0
2
Bit 2
0
1
Bit 1
0
0
Bit 0
0
Figure 19-33. Timer Input Capture/Output Compare Register 6 Low (TC6)
Module Base + 0x001E
R
W
Reset
15
Bit 15
0
14
Bit 14
0
13
Bit 13
0
12
Bit 12
0
11
Bit 11
0
10
Bit 10
0
9
Bit 9
0
8
Bit 8
0
Figure 19-34. Timer Input Capture/Output Compare Register 7 High (TC7)
MC9S12XHZ512 Data Sheet, Rev. 1.06
692
Freescale Semiconductor