S912XHZ512F1VAG Datasheet, PDF(417/978 Page) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

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S912XHZ512F1VAG Datasheet, PDF (417/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

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Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description

Module Base + 0x0004

7

R

FP23EN

W

Reset

0

6

5

4

3

2

1

FP22EN

FP21EN

FP20EN

FP19EN

FP18EN

FP17EN

0

0

0

0

0

0

Figure 10-6. LCD Frontplane Enable Register 2 (FPENR2)

0

FP16EN

0

Module Base + 0x0005

7

6

5

4

3

2

1

0

R

FP31EN

W

FP30EN

FP29EN

FP28EN

FP27EN

FP26EN

FP25EN

FP24EN

Reset

0

0

0

0

0

0

0

0

Figure 10-7. LCD Frontplane Enable Register 3 (FPENR3)

These bits enable the frontplane output waveform on the corresponding frontplane pin when LCDEN = 1.

Read: anytime

Write: anytime

Table 10-5. FPENR0âFPENR3 Field Descriptions

Field

Description

31:0

FP[31:0]EN

Frontplane Output Enable â The FP[31:0]EN bit enables the frontplane driver outputs. If LCDEN = 0, these

bits have no effect on the state of the I/O pins. It is recommended to set FP[31:0]EN bits before LCDEN is set.

0 Frontplane driver output disabled on FP[31:0].

1 Frontplane driver output enabled on FP[31:0].

10.3.2.4 LCD RAM (LCDRAM)

The LCD RAM consists of 16 bytes. After reset the LCD RAM contents will be indeterminate (I), as

indicated by Figure 10-8.

7

0x0008

LCDRAM

R

FP1BP3

W

Reset

I

0x0009

LCDRAM

R

FP3BP3

W

Reset

I

0x000A

LCDRAM

R

FP5BP3

W

Reset

I

I = Value is indeterminate

6

FP1BP2

I

FP3BP2

I

FP5BP2

I

5

FP1BP1

I

FP3BP1

I

FP5BP1

I

4

FP1BP0

I

FP3BP0

I

FP5BP0

I

3

FP0BP3

I

FP2BP3

I

FP4BP3

I

Figure 10-8. LCD RAM (LCDRAM)

2

FP0BP2

I

FP2BP2

I

FP4BP2

I

1

FP0BP1

I

FP2BP1

I

FP4BP1

I

0

FP0BP0

I

FP2BP0

I

FP4BP0

I

MC9S12XHZ512 Data Sheet, Rev. 1.06

Freescale Semiconductor

417

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