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| S912XHZ512F1VAG Datasheet, PDF (679/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256 | |||
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Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Register
Name
Bit 7
6
5
4
3
2
1
0x003A R TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC1H (High) W
0x003B R TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC1H (Low) W
0x003C R TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC2H (High) W
0x003D R TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC2H (Low) W
0x003E R TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC3H (High) W
0x003F R TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC3H (Low) W
= Unimplemented or Reserved
Figure 19-2. ECT Register Summary (Sheet 5 of 5)
19.3.2.1 Timer Input Capture/Output Compare Select Register (TIOS)
Bit 0
TC8
TC0
TC8
TC0
TC8
TC0
Module Base + 0x0000
R
W
Reset
7
IOS7
0
6
IOS6
0
5
IOS5
0
4
IOS4
0
3
IOS3
0
2
IOS2
0
1
IOS1
0
Figure 19-3. Timer Input Capture/Output Compare Register (TIOS)
Read or write: Anytime
All bits reset to zero.
Table 19-2. TIOS Field Descriptions
Field
7:0
IOS[7:0]
Description
Input Capture or Output Compare Channel Conï¬guration
0 The corresponding channel acts as an input capture.
1 The corresponding channel acts as an output compare.
0
IOS0
0
MC9S12XHZ512 Data Sheet Rev. 1.06
Freescale Semiconductor
679
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