S912XHZ512F1VAG Datasheet, PDF (767/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 22 S12X Debug (S12XDBGV3) Module
• TRIG Immediate software trigger independent of comparators
• Four trace modes
— Normal: change of flow (COF) PC information is stored (see Section 22.4.5.2.1) for change of
flow definition.
— Loop1: same as Normal but inhibits consecutive duplicate source address entries
— Detail: address and data for all cycles except free cycles and opcode fetches are stored
— Pure PC: All program counter addresses are stored.
• 4-stage state sequencer for trace buffer control
— Tracing session trigger linked to Final State of state sequencer
— Begin, End, and Mid alignment of tracing to trigger
22.1.4 Modes of Operation
The S12XDBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU12X monitoring is disabled.
Thus breakpoints, comparators, and CPU12X bus tracing are disabled but XGATE bus monitoring
accessing the S12XDBG registers, including comparator registers, is still possible. While in active BDM
or during hardware BDM accesses, XGATE activity can still be compared, traced and can be used to
generate a breakpoint to the XGATE module. When the CPU12X enters active BDM Mode through a
BACKGROUND command, with the S12XDBG module armed, the S12XDBG remains armed.
The S12XDBG module tracing is disabled if the MCU is secure. However, breakpoints can still be
generated if the MCU is secure.
BDM
Enable
x
0
0
1
1
BDM
Active
x
0
1
0
1
Table 22-3. Mode Dependent Restriction Summary
MCU
Secure
1
0
0
0
0
Comparator
Matches Enabled
Yes
Yes
Yes
XGATE only
Breakpoints
Possible
Tagging
Possible
Yes
Yes
Only SWI
Yes
Active BDM not possible when not enabled
Yes
Yes
XGATE only
XGATE only
Tracing
Possible
No
Yes
Yes
XGATE only
MC9S12XHZ512 Data Sheet Rev. 1.06
Freescale Semiconductor
767