S912XHZ512F1VAG Datasheet, PDF (684/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)
Module Base + 0x0008
7
R
OM7
W
6
OL7
5
OM6
4
OL6
3
OM5
2
OL5
1
OM4
0
OL4
Reset
0
0
0
0
0
0
0
0
Figure 19-11. Timer Control Register 1 (TCTL1)
Module Base + 0x0009
7
R
OM3
W
6
OL3
5
OM2
4
OL2
3
OM1
2
OL1
1
OM0
0
OL0
Reset
0
0
0
0
0
0
0
0
Figure 19-12. Timer Control Register 2 (TCTL2)
Read or write: Anytime
All bits reset to zero.
Table 19-9. TCTL1/TCTL2 Field Descriptions
Field
Description
OM[7:0]
7, 5, 3, 1
OL[7:0]
6, 4, 2, 0
OMx — Output Mode
OLx — Output Level
These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful
OCx compare. When either OMx or OLx is one, the pin associated with OCx becomes an output tied to OCx.
See Table 19-10.
Table 19-10. Compare Result Output Action
OMx
0
0
1
1
OLx
Action
0
No output compare
action on the timer output signal
1
Toggle OCx output line
0
Clear OCx output line to zero
1
Set OCx output line to one
NOTE
To enable output action by OMx and OLx bits on timer port, the
corresponding bit in OC7M should be cleared. The settings for these bits can
be seen in Table 19-11
MC9S12XHZ512 Data Sheet, Rev. 1.06
684
Freescale Semiconductor