S912XHZ512F1VAG Datasheet, PDF (733/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 20 Voltage Regulator (S12VREG3V3V5)
20.3.2.5 Autonomous Periodical Interrupt Rate High and Low Register
(VREGAPIRH / VREGAPIRL)
The VREGAPIRH and VREGAPIRL register allows the configuration of the VREG_3V3 autonomous
periodical interrupt rate.
Module Base + 0x0004
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
APIR11
0
2
APIR10
0
1
APIR9
0
Figure 20-6. Autonomous Periodical Interrupt Rate High Register (VREGAPIRH)
0
APIR8
0
Module Base + 0x0005
R
W
Reset
7
APIR7
0
6
APIR6
0
5
APIR5
0
4
APIR4
0
3
APIR3
0
2
APIR2
0
1
APIR1
0
Figure 20-7. Autonomous Periodical Interrupt Rate Low Register (VREGAPIRL)
0
APIR0
0
Table 20-7. VREGAPIRH / VREGAPIRL Field Descriptions
Field
Description
11-0
Autonomous Periodical Interrupt Rate Bits — These bits define the timeout period of the API. See Table 20-8
APIR[11:0] for details of the effect of the autonomous periodical interrupt rate bits. Writable only if APIFE = 0 of VREGAPICL
register.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
733