S912XHZ512F1VAG Datasheet, PDF (674/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.2.3 IOC5 — Input Capture and Output Compare Channel 5
This pin serves as input capture or output compare for channel 5.
19.2.4 IOC4 — Input Capture and Output Compare Channel 4
This pin serves as input capture or output compare for channel 4.
19.2.5 IOC3 — Input Capture and Output Compare Channel 3
This pin serves as input capture or output compare for channel 3.
19.2.6 IOC2 — Input Capture and Output Compare Channel 2
This pin serves as input capture or output compare for channel 2.
19.2.7 IOC1 — Input Capture and Output Compare Channel 1
This pin serves as input capture or output compare for channel 1.
19.2.8 IOC0 — Input Capture and Output Compare Channel 0
This pin serves as input capture or output compare for channel 0.
NOTE
For the description of interrupts see Section 19.4.3, “Interrupts”.
19.3 Memory Map and Register Definition
This section provides a detailed description of all memory and registers.
19.3.1 Module Memory Map
The memory map for the ECT module is given below in the Table 19-2. The address listed for each register
is the address offset. The total address for each register is the sum of the base address for the ECT module
and the address offset for each register.
19.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
MC9S12XHZ512 Data Sheet, Rev. 1.06
674
Freescale Semiconductor