S912XHZ512F1VAG Datasheet, PDF (68/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.1 Port A and Port B
Port A and port B are associated with the external address bus outputs ADDR15-ADDR0, the external read
visibility IVD15-IVD0 and the liquid crystal display (LCD) driver. Each pin is assigned to these functions
according to the following priority: LCD Driver > XEBI > general-purpose I/O.
If the corresponding LCD frontplane drivers are enabled (and LCD module is enabled), the FP[15:0]
outputs of the LCD module are available on port B and port A pins.
Refer to the LCD block description chapter for information on enabling and disabling the LCD and its
frontplane drivers.Refer to the S12X_EBI block description chapter for information on external bus.
During reset, port A and port B pins are configured as inputs with pull down.
2.3.1.1 Port A I/O Register (PTA)
Module Base + 0x0051
R
W
XEBI:
LCD:
Reset
7
PTA7
ADDR15
mux
IVD15
FP15
0
6
PTA6
ADDR14
mux
IVD14
FP14
0
5
PTA5
4
PTA4
3
PTA3
2
PTA2
ADDR13
mux
IVD13
ADDR12
mux
IVD12
ADDR11
mux
IVD11
ADDR10
mux
IVD10
FP13
FP12
FP11
FP10
0
0
0
0
Figure 2-2. Port A I/O Register (PTA)
1
PTA1
ADDR9
mux
IVD9
FP9
0
0
PTA0
ADDR8
mux
IVD8
FP8
0
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRAx) is set to 1 (output), a read returns the value of the I/O register
bit.
If the associated data direction bit (DDRAx) is set to 0 (input) and the LCD frontplane driver is enabled
(and LCD module is enabled), the associated I/O register bit (PTAx) reads “1”.
If the associated data direction bit (DDRAx) is set to 0 (input) and the LCD frontplane driver is disabled
(or LCD module is disabled), a read returns the value of the pin.
MC9S12XHZ512 Data Sheet, Rev. 1.06
68
Freescale Semiconductor