S912XHZ512F1VAG Datasheet, PDF (92/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.8.3 Port M Data Direction Register (DDRM)
Module Base + 0x0012
7
R
0
W
6
5
4
3
2
1
0
0
0
DDRM5
DDRM4
DDRM3
DDRM2
DDRM1
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-36. Port M Data Direction Register (DDRM)
Read: Anytime. Write: Anytime.
This register configures port pins PM[5:1] as either input or output.
When a CAN module is enabled, the corresponding transmitter (TXCANx) pin becomes an output, the
corresponding receiver (RXCANx) pin becomes an input, and the associated Data Direction Register bits
have no effect. If a CAN module is disabled, the corresponding Data Direction Register bit reverts to
control the I/O direction of the associated pin.
Table 2-26. DDRM Field Descriptions
Field
5:1
Data Direction Port M
DDRM[5:1] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
2.3.8.4 Port M Reduced Drive Register (RDRM)
Module Base + 0x0013
7
R
0
W
6
5
4
3
2
1
0
0
0
RDRM5
RDRM4
RDRM3
RDRM2
RDRM1
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-37. Port M Reduced Drive Register (RDRM)
Read: Anytime. Write: Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
MC9S12XHZ512 Data Sheet, Rev. 1.06
92
Freescale Semiconductor