S912XHZ512F1VAG Datasheet, PDF (90/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.7.6 Port L Polarity Select Register (PPSL)
Module Base + 0x0035
7
R
PPSL7
W
6
PPSL6
5
PPSL5
4
PPSL4
3
PPSL3
2
PPSL2
1
PPSL1
0
PPSL0
Reset
1
1
1
1
1
1
1
1
Figure 2-32. Port L Polarity Select Register (PPSL)
Read: Anytime. Write: Anytime.
The Port L Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin.
The Port L Polarity Select Register is effective only when the corresponding Data Direction Register bit
is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1.
Table 2-24. PPSL Field Descriptions
Field
Description
7:0
Pull Select Port L
PPSL[7:0] 0 A pull-up device is connected to the associated port L pin.
1 A pull-down device is connected to the associated port L pin.
2.3.7.7 Port L Slew Rate Register (SRRL)
Module Base + 0x003B
R
W
Reset
7
SRRL7
0
6
SRRL6
5
SRRL5
4
SRRL4
3
SRRL3
2
SRRL2
0
0
0
0
0
Figure 2-33. Port L Slew Rate Register (SRRL)
1
SRRL1
0
0
SRRL0
0
Read: Anytime. Write: Anytime.
This register enables the slew rate control and disables the digital input buffer for port pins PL[7:0].
Table 2-25. SRRL Field Descriptions
Field
Description
7:0
Slew Rate Port L
SRRL[7:0] 0 Disables slew rate control and enables digital input buffer.
1 Enables slew rate control and disables digital input buffer.
MC9S12XHZ512 Data Sheet, Rev. 1.06
90
Freescale Semiconductor