S912XHZ512F1VAG Datasheet, PDF (106/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.10.8 Port S Slew Rate Register (SRRS)
Module Base + 0x003B
R
W
Reset
7
SRRS7
0
6
SRRS6
5
SRRS5
4
SRRS4
3
SRRS3
2
SRRS2
0
0
0
0
0
Figure 2-57. Port S Slew Rate Register (SRRS)
1
SRRS1
0
0
SRRS0
0
Read: Anytime. Write: Anytime.
This register enables the slew rate control and disables the digital input buffer for port pins PS[7:0].
Table 2-43. SRRS Field Descriptions
Field
Description
7:0
Slew Rate Port S
SRRS[7:0] 0 Disables slew rate control and enables digital input buffer.
1 Enables slew rate control and disables digital input buffer.
MC9S12XHZ512 Data Sheet, Rev. 1.06
106
Freescale Semiconductor