S912XHZ512F1VAG Datasheet, PDF (22/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 1 MC9S12XHZ Family Device Overview
1.1.1 Features
• HCS12X Core
— 16-bit HCS12X CPU
– Upward compatible with MC9S12 instruction set
– Interrupt stacking and programmer’s model identical to MC9S12
– Instruction queue
– Enhanced indexed addressing
– Enhanced instruction set
— EBI (external bus interface)
— MMC (module mapping control)
— INT (interrupt controller)
— DBG (debug module to monitor HCS12X CPU and XGATE bus activity)
— BDM (background debug mode)
• XGATE (peripheral coprocessor)
— Parallel processing module off loads the CPU by providing high-speed data processing and
transfer
— Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports
• Memory
– 512K, 384K, 256K byte Flash EEPROM
– 4K byte EEPROM
– 32K, 28K, 16K byte RAM
• CRG (clock and reset generator)
— Low noise/low power Pierce oscillator
— PLL
— COP watchdog
— Real time interrupt
— Clock monitor
— Fast wake-up from stop mode
• Analog-to-digital converter
— 16 channels, 10-bit resolution
— External conversion trigger capability
• ECT (enhanced capture timer)
— 16-bit main counter with 8-bit prescaler
— 8 programmable input capture or output compare channels
— Four 8-bit or two 16-bit pulse accumulators
• PIT (periodic interrupt timer)
— Four timers with independent time-out periods
— Time-out periods selectable between 1 and 2²⁴ bus clock cycles
MC9S12XHZ512 Data Sheet, Rev. 1.06
22
Freescale Semiconductor