S912XHZ512F1VAG Datasheet, PDF (437/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 11 Motor Controller (MC10B12CV2) Block Description
11.3.2.2 Motor Controller Control Register 1
This register controls the behavior of the analog section of the motor controller as well as the interrupt
enables.
Offset Module Base + 0x0001
7
6
5
4
3
2
1
R
0
0
0
0
0
0
RECIRC
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-4. Motor Controller Control Register 1 (MCCTL1)
Table 11-5. MCCTL1 Field Descriptions
0
MCTOIE
0
Field
7
RECIRC
0
MCTOIE
Description
Recirculation in (Dual) Full H-Bridge Mode (refer to Section 11.4.1.3.3, “RECIRC Bit”)— RECIRC only
affects the outputs in (dual) full H-bridge modes. In half H-bridge mode, the PWM output is always active low.
RECIRC = 1 will also invert the effect of the S bits (refer to Section 11.4.1.3.2, “Sign Bit (S)”) in (dual) full
H-bridge modes. RECIRC must be changed only while no PWM channel is operating in (dual) full H-bridge
mode; otherwise, erroneous output pattern may occur.
0 Recirculation on the high side transistors. Active state for PWM output is logic low, the static channel will
output logic high.
1 Recirculation on the low side transistors. Active state for PWM output is logic high, the static channel will
output logic low.
Motor Controller Timer Counter Overflow Interrupt Enable
0 Interrupt disabled.
1 Interrupt enabled. An interrupt will be generated when the motor controller timer counter overflow interrupt flag
(MCTOIF) is set.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
437