S912XHZ512F1VAG Datasheet, PDF (421/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description
• 1/3 duty (3 backplanes), 1/3 bias (4 voltage levels)
• 1/4 duty (4 backplanes), 1/3 bias (4 voltage levels)
The voltage levels required for the different operating modes are generated internally based on VLCD.
Changing VLCD alters the differential RMS voltage across the segments in the ON and OFF states,
thereby setting the display contrast.
The backplane waveforms are continuous and repetitive every frame. They are fixed within each operating
mode and are not affected by the data in the LCD RAM.
The frontplane waveforms generated are dependent on the state (ON or OFF) of the LCD segments as
defined in the LCD RAM. The LCD32F4BV1 driver hardware uses the data in the LCD RAM to construct
the frontplane waveform to create a differential RMS voltage necessary to turn the segment ON or OFF.
The LCD duty is decided by the DUTY1 and DUTY0 bits in the LCD control register 0 (LCDCR0). The
number of bias voltage levels is determined by the BIAS bit in LCDCR0. Table 10-8 summarizes the
multiplex modes (duties) and the bias voltage levels that can be selected for each multiplex mode (duty).
The backplane pins have their corresponding backplane waveform output BP[3:0] in high impedance state
when in the OFF state as indicated in Table 10-8. In the OFF state the corresponding pins BP[3:0]can be
used for other functionality, for example as general purpose I/O ports.
Duty
1/1
1/2
1/3
1/4
LCDCR0 Register
DUTY1
0
1
1
0
DUTY0
1
0
1
0
Table 10-8. LCD Duty and Bias
Backplanes
Bias (BIAS = 0)
BP3 BP2 BP1 BP0 1/1
1/2
1/3
OFF OFF OFF BP0 YES NA
NA
OFF OFF BP1 BP0 NA YES NA
OFF BP2 BP1 BP0 NA
NA YES
BP3 BP2 BP1 BP0 NA
NA YES
Bias (BIAS = 1)
1/1 1/2 1/3
YES NA NA
NA NA YES
NA NA YES
NA NA YES
10.4.2 Operation in Wait Mode
The LCD32F4BV1 driver system operation during wait mode is controlled by the LCD stop in wait
(LCDSWAI) bit in the LCD control register 1 (LCDCR1). If LCDSWAI is reset, the LCD32F4BV1 driver
system continues to operate during wait mode. If LCDSWAI is set, the LCD32F4BV1 driver system is
turned off during wait mode. In this case, the LCD waveform generation clocks are stopped and the
LCD32F4BV1 drivers pull down to VSSX those frontplane and backplane pins that were enabled before
entering wait mode. The contents of the LCD RAM and the LCD registers retain the values they had prior
to entering wait mode.
10.4.3 Operation in Pseudo Stop Mode
The LCD32F4BV1 driver system operation during pseudo stop mode is controlled by the LCD run in
pseudo stop (LCDRPSTP) bit in the LCD control register 1 (LCDCR1). If LCDRPSTP is reset, the
LCD32F4BV1 driver system is turned off during pseudo stop mode. In this case, the LCD waveform
generation clocks are stopped and the LCD32F4BV1 drivers pull down to VSSX those frontplane and
backplane pins that were enabled before entering pseudo stop mode. If LCDRPSTP is set, the
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
421