S912XHZ512F1VAG Datasheet, PDF (706/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Field
6
PBEN
1
PBOVI
Table 19-37. PBCTL Field Descriptions
Description
Pulse Accumulator B System Enable — PBEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
0 16-bit pulse accumulator system disabled. 8-bit PAC1 and PAC0 can be enabled when their related enable
bits in ICPAR are set.
1 Pulse accumulator B system enabled. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form
the PACB 16-bit pulse accumulator B. When PACB is enabled, the PACN1 and PACN0 registers contents are
respectively the high and low byte of the PACB.
PA1EN and PA0EN control bits in ICPAR have no effect.
The PACB shares the input pin with IC0.
Pulse Accumulator B Overflow Interrupt Enable
0 Interrupt inhibited
1 Interrupt requested if PBOVF is set
19.3.2.29 Pulse Accumulator B Flag Register (PBFLG)
Module Base + 0x0031
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
PBOVF
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-52. Pulse Accumulator B Flag Register (PBFLG)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the flag cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference Section 19.3.2.6, “Timer
System Control Register 1 (TSCR1)”.
All bits reset to zero.
PBFLG indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA
bit in Section 19.3.2.6, “Timer System Control Register 1 (TSCR1)”).
Table 19-38. PBFLG Field Descriptions
Field
1
PBOVF
Description
Pulse Accumulator B Overflow Flag — This bit is set when the 16-bit pulse accumulator B overflows from
0xFFFF to 0x0000, or when 8-bit pulse accumulator 1 (PAC1) overflows from 0x00FF to 0x0000.
When PACMX = 1, PBOVF bit can also be set if 8-bit pulse accumulator 1 (PAC1) reaches 0x00FF and an active
edge follows on IC1.
MC9S12XHZ512 Data Sheet, Rev. 1.06
706
Freescale Semiconductor