S912XHZ512F1VAG Datasheet, PDF(54/978 Page) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

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S912XHZ512F1VAG Datasheet, PDF (54/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

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Chapter 1 MC9S12XHZ Family Device Overview

Table 1-9. Interrupt Vector Locations (Sheet 3 of 3)

Vector Address1

XGATE

Channel ID2

Interrupt Source

CCR

Mask

Vector base + 0x78

0x3C

Periodic interrupt timer channel 1

I bit

Vector base + 0x76

Vector base + 0x74

Vector base + 0x72

Vector base + 0x70

0x3B

0x3A

0x39

0x38

Periodic interrupt timer channel 2

I bit

Periodic interrupt timer channel 3

I bit

XGATE software trigger 0

I bit

XGATE software trigger 1

I bit

Vector base + 0x6E

Vector base + 0x6C

Vector base + 0x6A

Vector base + 0x68

Vector base + 0x66

0x37

0x36

0x35

0x34

0x33

XGATE software trigger 2

I bit

XGATE software trigger 3

I bit

XGATE software trigger 4

I bit

XGATE software trigger 5

I bit

XGATE software trigger 6

I bit

Vector base + 0x64

Vector base + 0x62

Vector base + 0x60

Vector base+ 0x12

to

Vector base + 0x5E

0x32

â

â

â

XGATE software trigger 7

I bit

XGATE software error interrupt

I bit

S12XCPU RAM access violation

I bit

Reserved

â

Vector base + 0x10

â

Spurious interrupt

â

1 16 bits vector address based

2 For detailed description of XGATE channel ID refer to XGATE block description chapter

Local Enable

PITINTE (PINTE1)

PITINTE (PINTE2)

PITINTE (PINTE3)

XGMCTL (XGIE)

XGMCTL (XGIE)

XGMCTL (XGIE)

XGMCTL (XGIE)

XGMCTL (XGIE)

XGMCTL (XGIE)

XGMCTL (XGIE)

XGMCTL (XGIE)

XGMCTL (XGIE)

RAMWPC (AVIE)

Reserved

None

1.6.2 Effects of Reset

When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the

respective module block description chapters for register reset states.

1.6.2.1 I/O Pins

Refer to the PIM block description chapter for reset conï¬gurations of all peripheral module ports.

1.6.2.2 Memory

The RAM array is not initialized out of reset.

1.7 COP Conï¬guration

The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge

of RESET from the Flash control register FCTL (0x0107) located in the Flash EEPROM block. See

Table 1-10 and Table 1-11 for coding. The FCTL register is loaded from the Flash conï¬guration ï¬eld byte

at global address 0x7FFF0E during the reset sequence

MC9S12XHZ512 Data Sheet, Rev. 1.06

54

Freescale Semiconductor

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