S912XHZ512F1VAG Datasheet, PDF (731/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 20 Voltage Regulator (S12VREG3V3V5)
20.3.2.3 Autonomous Periodical Interrupt Control Register (VREGAPICL)
The VREGAPICL register allows the configuration of the VREG_3V3 autonomous periodical interrupt
features.
Module Base + 0x0002
7
6
5
4
R
0
0
0
APICLK
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
2
1
0
APIFE
APIE
0
0
0
Figure 20-4. Autonomous Periodical Interrupt Control Register (VREGAPICL)
0
APIF
0
Table 20-4. VREGAPICL Field Descriptions
Field
7
APICLK
2
APIFE
1
APIE
0
APIF
Description
Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source for the API. Writable only if
APIFE = 0; APICLK cannot be changed if APIFE is set by the same write operation.
0 Autonomous periodical interrupt clock used as source.
1 Bus clock used as source.
Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer
when set.
0 Autonomous periodical interrupt is disabled.
1 Autonomous periodical interrupt is enabled and timer starts running.
Autonomous Periodical Interrupt Enable Bit
0 API interrupt request is disabled.
1 API interrupt will be requested whenever APIF is set.
Autonomous Periodical Interrupt Flag — APIF is set to 1 when the in the API configured time has elapsed.
This flag can only be cleared by writing a 1 to it. Clearing of the flag has precedence over setting.
Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request.
0 API timeout has not yet occurred.
1 API timeout has occurred.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
731