SH7729R Datasheet, PDF (97/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Instruction Format
Source
Operand
Destination
Operand
Sample Instruction
nm type
15
0
xxxx nnnn mmmm xxxx
md type
15
0
xxxx xxxx mmmm dddd
mmmm: register
direct
nnnn: register
direct
ADD Rm,Rn
mmmm: register
indirect
nnnn: register
indirect
MOV.L Rm,@Rn
mmmm: post-
increment register
indirect (multiply-
and-accumulate
operation)
MACH, MACL
MAC.W @Rm+,@Rn+
nnnn: * post-
increment register
indirect (multiply-
and-accumulate
operation)
mmmm: post-
nnnn: register
increment register direct
indirect
MOV.L @Rm+,Rn
mmmm: register
direct
nnnn: pre-
MOV.L Rm,@-Rn
decrement register
indirect
mmmm: register
direct
nnnn: indexed
register indirect
MOV.L Rm,@(R0,Rn)
mmmmdddd:
R0 (register direct) MOV.B @(disp,Rm),R0
register indirect
with displacement
nd4 type
15
xxxx xxxx
nnnn
0
dddd
R0 (register direct) nnnndddd:
register indirect
with displacement
MOV.B R0,@(disp,Rn)
nmd type
15
0
xxxx nnnn mmmm dddd
mmmm: register
direct
mmmmdddd:
register indirect
with displacement
nnnndddd:
register indirect
with displacement
nnnn: register
direct
MOV.L Rm,@(disp,Rn)
MOV.L @(disp,Rm),Rn
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
Rev. 5.0, 09/03, page 51 of 806