SH7729R Datasheet, PDF (33/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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Block Diagram ..................................................................................................... 7
Pin Assignment (FP-208C, FP-208E) .................................................................. 8
Pin Assignment (BP-240A).................................................................................. 9
Register Configuration in Each Processing Mode (1) .......................................... 21
Register Configuration in Each Processing Mode (2) .......................................... 22
General Purpose Registers (Not in DSP Mode) ................................................... 23
General Purpose Registers (DSP Mode) .............................................................. 24
Control Registers.................................................................................................. 27
System Registers .................................................................................................. 30
DSP Registers....................................................................................................... 32
Connections of DSP Registers and Buses ............................................................ 34
Longword Operand .............................................................................................. 35
Data Formats ........................................................................................................ 36
Byte, Word, and Longword Alignment ................................................................ 37
X and Y Data Transfer Addressing ...................................................................... 46
Single Data Transfer Addressing.......................................................................... 47
Modulo Addressing .............................................................................................. 48
DSP Instruction Formats ...................................................................................... 53
Sample Parallel Instruction Program.................................................................... 80
Examples of Conditional Operations and Data Transfer Instructions .................. 88
MMU Functions ................................................................................................... 93
Virtual Address Space Mapping........................................................................... 95
MMU Register Contents ...................................................................................... 98
Overall Configuration of the TLB ........................................................................ 99
Virtual Address and TLB Structure...................................................................... 100
TLB Indexing (IX = 1) ......................................................................................... 101
TLB Indexing (IX = 0) ......................................................................................... 102
Objects of Address Comparison ........................................................................... 103
Operation of LDTLB Instruction.......................................................................... 107
Synonym Problem ................................................................................................ 109
MMU Exception Generation Flowchart ............................................................... 114
MMU Exception Signals in Instruction Fetch ...................................................... 115
MMU Exception Signals in Data Access ............................................................. 116
MMU Exception in Repeat Loop ......................................................................... 117
Specifying Address and Data for Memory-Mapped TLB Access ........................ 120
Vector Table......................................................................................................... 124
Example of Acceptance Order of General Exceptions ......................................... 127
Bit Configurations of EXPEVT, INTEVT, INTEVT2, and TRA Registers......... 130
Cache Structure .................................................................................................... 144
CCR Register Configuration ................................................................................ 146
CCR2 Register Configuration .............................................................................. 147
Cache Search Scheme (Normal Mode) ................................................................ 149
Rev. 5.0, 09/03, page xxxiii of xlvi