SH7729R Datasheet, PDF (253/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

8.2.9 Break Control Register (BRCR)
Bit: 31
30
29
28
27
26
25
24
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
—
— BASMA BASMB —
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R/W R/W
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
SCMFCA SCMFCB SCMFDA SCMFDB PCTE PCBA —
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W
R
R
Bit: 7
6
5
DBEB PCBB —
Initial value: 0
0
0
R/W: R/W R/W
R
4
3
2
—
SEQ
—
0
0
0
R
R/W
R
1
0
—
ETBE
0
0
R
R/W
BRCR sets the following conditions:
1. Use of channels A and B as two independent channel conditions or as a sequential condition
2. Break setting before or after instruction execution
3. Break setting by the number of execution times
4. Determination of whether to include data bus on channel B in comparison conditions
5. Enabling of PC trace
6. Enabling of ASID check
The break control register (BRCR) is a 32-bit readable/writable register that has break condition
match flags and bits for setting a variety of break conditions.
BRCR is initialized to H'00000000 by a power-on reset.
Rev. 5.0, 09/03, page 207 of 806