SH7729R Datasheet, PDF (22/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

7.2.6 Interrupt Exception Handling and Priority ........................................................... 169
7.3 INTC Registers.................................................................................................................. 175
7.3.1 Interrupt Priority Registers A to E (IPRA–IPRE) ................................................ 175
7.3.2 Interrupt Control Register 0 (ICR0) ..................................................................... 176
7.3.3 Interrupt Control Register 1 (ICR1) ..................................................................... 177
7.3.4 Interrupt Control Register 2 (ICR2) ..................................................................... 180
7.3.5 PINT Interrupt Enable Register (PINTER) .......................................................... 181
7.3.6 Interrupt Request Register 0 (IRR0)..................................................................... 182
7.3.7 Interrupt Request Register 1 (IRR1)..................................................................... 184
7.3.8 Interrupt Request Register 2 (IRR2)..................................................................... 185
7.4 INTC Operation................................................................................................................. 187
7.4.1 Interrupt Sequence................................................................................................ 187
7.4.2 Multiple Interrupts................................................................................................ 189
7.5 Interrupt Response Time ................................................................................................... 189
Section 8 User Break Controller...................................................................................... 193
8.1 Overview ........................................................................................................................... 193
8.1.1 Features ................................................................................................................ 193
8.1.2 Block Diagram ..................................................................................................... 195
8.1.3 Register Configuration ......................................................................................... 196
8.2 Register Descriptions......................................................................................................... 197
8.2.1 Break Address Register A (BARA)...................................................................... 197
8.2.2 Break Address Mask Register A (BAMRA) ........................................................ 198
8.2.3 Break Bus Cycle Register A (BBRA) .................................................................. 199
8.2.4 Break Address Register B (BARB) ...................................................................... 201
8.2.5 Break Address Mask Register B (BAMRB)......................................................... 202
8.2.6 Break Data Register B (BDRB) ........................................................................... 203
8.2.7 Break Data Mask Register B (BDMRB) .............................................................. 204
8.2.8 Break Bus Cycle Register B (BBRB)................................................................... 205
8.2.9 Break Control Register (BRCR)........................................................................... 207
8.2.10 Break Execution Times Register (BETR) ............................................................ 210
8.2.11 Branch Source Register (BRSR) .......................................................................... 211
8.2.12 Branch Destination Register (BRDR) .................................................................. 213
8.2.13 Break ASID Register A (BASRA) ....................................................................... 214
8.2.14 Break ASID Register B (BASRB) ....................................................................... 214
8.3 Operation Description ....................................................................................................... 215
8.3.1 Flow of the User Break Operation........................................................................ 215
8.3.2 Break on Instruction Fetch Cycle ......................................................................... 215
8.3.3 Break by Data Access Cycle ................................................................................ 216
8.3.4 Break on X/Y-Memory Bus Cycle ....................................................................... 217
8.3.5 Sequential Break .................................................................................................. 217
8.3.6 Value of Saved Program Counter......................................................................... 217
8.3.7 PC Trace............................................................................................................... 218
Rev. 5.0, 09/03, page xxii of xlvi