SH7729R Datasheet, PDF (174/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

4.2.4 Exception Codes
Table 4.3 lists the exception codes written to EXPEVT register (for reset or general exceptions) or
the INTEVT and INTEVT2 registers (for general interrupt requests) to identify each specific
exception event.
Table 4.3 Exception Codes
Exception Type
Reset
General exception events
General interrupt requests
Exception Event
Power-on reset
Manual reset
UDI reset
TLB miss/invalid (read)
TLB miss/invalid (write)
TLB miss/invalid/CPU Address error in
repeat loop
Initial page write
TLB protection violation (read)
TLB protection violation (write)
TLB protection violation in repeat loop
CPU address error (read)
CPU address error (write)
Unconditional trap (TRAPA instruction)
Illegal general instruction exception
Illegal slot instruction exception
User breakpoint trap
DMA address error
Nonmaskable interrupt
UDI interrupt
External hardware interrupts:
IRL3–IRL0 = 0000
IRL3–IRL0 = 0001
Exception Code
H'000
H'020
H'000
H'040
H'060
H'070
H'080
H'0A0
H'0C0
H'0D0
H'0E0
H'100
H'160
H'180
H'1A0
H'1E0
H'5C0
H'1C0
H'5E0
H'200
H'220
Rev. 5.0, 09/03, page 128 of 806