SH7729R Datasheet, PDF (544/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 15.9 Serial Mode Register Settings and SCI Communication Formats
SCSMR Settings
SCI Communication Format
Bit 7 Bit 6 Bit 5 Bit 2 Bit 3
C/A CHR PE MP STOP Mode
Data Parity Multipro- Stop Bit
Length Bit
cessor Bit Length
00
0
0
0
Asynchronous 8-bit
Not set Not set 1 bit
1
2 bits
1
0
Set
1 bit
1
2 bits
1
0
0
7-bit
Not set
1 bit
1
2 bits
1
0
Set
1 bit
1
2 bits
0
*
1
0
*
1
1
*
0
Asynchronous 8-bit
(multiprocessor
format)
7-bit
Not set Set
1 bit
2 bits
1 bit
*
1
2 bits
1*
*
*
*
Synchronous 8-bit
Not set None
Note: Asterisks (*) indicate don’t care bits.
Table 15.10 SCSMR and SCSCR Settings and SCI Clock Source Selection
SCSMR
Bit 7
C/A
0
1
SCSCR Settings
Bit 1 Bit 0
CKE1 CKE0
Mode
0
0
1
Asynchronous
mode
1
0
1
0
0
1
1
0
1
Synchronous
mode
SCI Transmit/Receive Clock
Clock
Source
SCK
Pin Function
Internal
SCI does not use the SCK pin
Outputs a clock with frequency
matching the bit rate
External
Inputs a clock with frequency 16
times the bit rate
Internal
Outputs the serial clock
External
Inputs the serial clock
Rev. 5.0, 09/03, page 498 of 806