SH7729R Datasheet, PDF (444/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

(2) In indirect address transfer mode, the address of memory in which data to be transferred is
stored is specified in the transfer source address register (SAR3) in the DMAC. 16-byte
transfer is not possible. Consequently, in this mode, the address value specified in the
transfer source address register in the DMAC is read first. This value is temporarily
stored in the DMAC. Next, the read value is output as an address, and the value stored in
that address is stored in the DMAC again. Then, the value read afterwards is written to
the address specified in the transfer destination address; this completes one DMA transfer.
Figure 12.9 shows an example. In this example, the transfer destination, the transfer
source, and the storage destination of the indirect address are external memories, and
transfer data is 16 or 8 bits. Figure 12.10 shows an example of the transfer timing.
In this mode, one NOP cycle (CK1 cycle shown in figure 12.10) is required to output data
read as an indirect address to an address bus.
If transfer data is 32 bits, the third and fourth bus cycles shown in figure 12.10 are
required twice for each; a total of six bus cycles and one NOP cycle are required.
Rev. 5.0, 09/03, page 398 of 806