SH7729R Datasheet, PDF (204/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

6.2 X/Y Memory Access from CPU
The X/Y memory can be located in either a mappable area or fixed-mapped area, depending on the
mode bit (MD) and DSP bit (DSP) setting in the status register (SR). Figure 6.1 shows X/Y
memory logical mapping.
1. Privileged Mode
MD = 1, DSP = 0: Any physical address in space P0 or P3 can map to X/Y memory through
TLB translation. Addresses ranging from H'A500 0000 to H'A5FF FFFF in the P2 space can
also fixed-map to X/Y memory. Since the DSP extension is disabled, the DSP instruction set
and registers are not available to the programmer.
2. User Mode
MD = 0, DSP = 0: Any physical address in the U0 space can access X/Y memory through TLB
translation. Any access to addresses beyond the U0 space will cause an address error. Since the
DSP extension is disabled, the DSP instruction set and registers are not available to the
programmer.
3. Privileged-DSP Mode
MD = 1, DSP = 1: Any physical address in space P0 or P3 can map to X/Y memory through
TLB translation. Addresses ranging from H'A500 0000 to H'A5FF FFFF in the P2 space can
also fixed-map to X/Y memory. Since the DSP extension is enabled, the DSP instruction set
and registers are available to the programmer.
4. User-DSP Mode
MD = 0, DSP = 1: Any physical address in space U0 can map to X/Y memory through TLB
translation. Addresses ranging from H'A500 0000 to H'A5FF FFFF in the Uxy spaces can also
fixed-map to X/Y memory. Any access outside U0 and Uxy space will cause an address error.
Since the DSP extension is enabled, the DSP instruction set and registers are available to the
programmer.
For the mappable area, the C (cacheable) bit in the TLB entry must be cleared to 0 to guarantee a
two-cycle access.
Mapping through TLB translation provides a flexible X/Y memory addressing scheme but takes
two cycles even when the C bit in the TLB entry is cleared to 0. Fixed mapping provides a one-
cycle access for read and two-cycle access for write, which is the appropriate method for mission-
critical realtime operations.
The X/Y memory resides in the second 16 Mbytes of physical address space area 1, from H'A500
0000 to H'A5FF FFFF. This 16-Mbyte address space is shadowed and maps to the same 128-kbyte
X/Y ROM/RAM. Figures 6.1 and 6.2 show X/Y memory physical mapping.
Rev. 5.0, 09/03, page 158 of 806