SH7729R Datasheet, PDF (337/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

11.2.5 Individual Memory Control Register (MCR)
The individual memory control register (MCR) is a 16-bit readable/writable register that specifies
RAS and CAS timing and burst control for synchronous DRAM (areas 2 and 3), specifies address
multiplexing, and controls refresh. This enables direct connection of synchronous DRAM without
external circuits.
MCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode. Bits TPC1–TPC0, RCD1–RCD0, TRWL1–TRWL0, TRAS1–TRAS0, RASD, BE,
AMX2–AMX0, and EDOMODE are written to in the initialization after a power-on reset and
should not then be modified again. When RFSH and RMODE are written to, write the same values
to the other bits. When using synchronous DRAM, do not access areas 2 and 3 until this register is
initialized.
Bit:
Initial value:
R/W:
15
TPC1
0
R/W
14
TPC0
0
R/W
13
RCD1
0
R/W
12
RCD0
0
R/W
11
10
9
TRWL1 TRWL0 TRAS1
0
0
0
R/W R/W R/W
8
TRAS0
0
R/W
Bit: 7
6
5
4
3
2
1
0
RASD AMX3 AMX2 AMX1 AMX0 RFSH RMODE ^—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W
R
Bits 15 and 14—RAS Precharge Time (TPC1, TPC0): When synchronous DRAM interface is
selected as connected memory, they set the minimum number of cycles until output of the next
bank-active command after precharge. However, the number of cycles input immediately after the
issue of an all-bank-precharge command (PALL) in the case of an auto-refresh or a precharge
command (PRE) in the bank active mode is one fewer than the normal value. TPC1 should not be
set to 0 and TPC0 to 1 in the bank active mode.
Description
Bit 15:
TPC1
Bit 14:
TPC0
Normal Operation
Immediately after
Immediately after
Precharge Command^* Self-Refresh
0
0
1 cycle (Initial value) 0 cycle (Initial value) 2 cycles (Initial value)
1
2 cycles
1 cycle
5 cycles
1
0
3 cycles
2 cycles
8 cycles
1
4 cycles
3 cycles
11 cycles
Note: * Immediately after all-bank-precharge (PALL) in the case of an auto-refresh or precharge
(PRE) in the bank active mode.
Rev. 5.0, 09/03, page 291 of 806