SH7729R Datasheet, PDF (574/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

15.4 SCI Interrupts
The SCI has four interrupt sources transmit-end (TEI), receive-error (ERI), receive-data-full
(RXI), and transmit-data-empty (TXI). Table 15.13 lists the interrupt sources and indicates their
priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial
control register (SCSCR). Each interrupt request is sent separately to the interrupt controller.
TXI is requested when the TDRE bit in SCSSR is set to 1. TDRE is automatically cleared to 0
when data is written in the transmit data register (SCTDR).
RXI is requested when the RDRF bit in SCSSR is set to 1. RDRF is automatically cleared to 0
when the receive data register (SCRDR) is read.
ERI is requested when the ORER, PER, or FER bit in SCSSR is set to 1.
TEI is requested when the TEND bit in SCSSR is set to 1. Where the TXI interrupt indicates that
transmit data writing is enabled, the TEI interrupt indicates that the transmit operation is complete.
Table 15.13 SCI Interrupt Sources
Interrupt Source
ERI
RXI
TXI
TEI
Description
Receive error (ORER, PER, or FER)
Receive data full (RDRF)
Transmit data empty (TDRE)
Transmit end (TEND)
Priority When Reset Is Cleared
High
Low
See section 4, Exception Handling, for priorities and the relationship to non-SCI interrupts.
Rev. 5.0, 09/03, page 528 of 806