SH7729R Datasheet, PDF (501/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

14.2 RTC Registers
14.2.1 64-Hz Counter (R64CNT)
The 64-Hz counter (R64CNT) is an 8-bit read-only register that indicates the state of the RTC
divider circuit between 64 Hz and 1 Hz.
R64CNT is reset to H'00 by setting the RESET bit in RTC control register 2 (RCR2) or the ADJ
bit in RCR2 to 1.
R64CNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit 7 is always read as 0.
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
1Hz
2Hz
4Hz
8Hz 16Hz 32Hz 64Hz
—
—
—
—
—
—
—
R
R
R
R
R
R
R
14.2.2 Second Counter (RSECCNT)
The second counter (RSECCNT) is an 8-bit readable/writable register used for setting/counting in
the BCD-coded second section of the RTC. The count operation is performed by a carry for each
second of the 64-Hz counter.
The range that can be set is 00–59 (decimal). Errant operation will result if any other value is set.
Carry out write processing after halting the count operation with the START bit in RCR2.
RSECCNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
10 seconds
1 second
—
—
—
—
—
—
—
R/W R/W R/W R/W R/W R/W R/W
Rev. 5.0, 09/03, page 455 of 806