SH7729R Datasheet, PDF (161/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

3.5.5
Processing Flow in Event of MMU Exception (Same Processing Flow for Address
Error)
MMU Exception in Instruction Fetch Mode
TLB-related exception signals in an instruction fetch
IF ID EX MA WB
ID EX MA WB
ID EX MA WB
Handler transition
processing
NOP
NOP
MMU exception handler
IF ID EX MA WB
: Exception source stage
IF = Instruction fetch
ID = Instruction decode
EX = Instruction execution
MA = Memory access
WB = Write back
NOP = No operation
Figure 3.12 MMU Exception Signals in Instruction Fetch
Rev. 5.0, 09/03, page 115 of 806