SH7729R Datasheet, PDF (466/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

12.4 Compare Match Timer (CMT)
12.4.1 Overview
The DMAC has an on-chip compare match timer (CMT) to generate DMA transfer requests. The
CMT has a 16-bit counter.
Features
The CMT has the following features:
• Four types of counter input clock can be selected
 One of four internal clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) can be selected.
• Generates a DMA transfer request when compare match occurs.
Block Diagram
Figure 12.26 shows a block diagram of the CMT.
Pφ/4 Pφ/8 Pφ/16 Pφ/64
Control circuit
Clock selection
CMT
Module bus
Bus
interface
CMSTR: Compare match timer start register
CMCSR0: Compare match timer control/status register 0
CMCOR0: Compare match timer constant register 0
CMCNT0: Compare match timer counter 0
Internal bus
Figure 12.26 Block Diagram of CMT
Rev. 5.0, 09/03, page 420 of 806