SH7729R Datasheet, PDF (763/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Item
Symbol Min Max Unit Figure
ICIORD delay time
ICIOWR delay time
IOIS16 setup time
IOIS16 hold time
DACK delay time 1
(Based on CKLO rise)
tICRSD
tICWSD
tIO16S
tIO16H
tDAKD1
— 10 ns 24.44–24.46
— 10 ns 24.44–24.46
6 — ns 24.45, 24.46
4 — ns 24.45, 24.46
— 10 ns 24.16–24.36, 24.39–24.46
DACK delay time 2
(Based on CKLO fall)
tDAKD2
— 10 ns 24.16–24.21
Notes: 1. Specified based on the slowest negate timing for CSn, RD, or WEn.
2. Specified based on whichever negate timing is faster, CSn or RD.
Rev. 5.0, 09/03, page 717 of 806