SH7729R Datasheet, PDF (417/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

12.1.2 Block Diagram
Figure 12.1 shows a block diagram of the DMAC.
X/Y
memory
On-chip
peripheral
module
DMAC module
Iteration
control
SARn
Register
control
Start-up
control
DARn
DMATCRn
CHCRn
DREQ0, DREQ1
IrDA, SCIF
A/D converter
CMT
DEIn
DACK0, DACK1
DRAK0, DRAK1
Request
priority
control
DMAOR
External
ROM
External
RAM
Bus interface
External I/O
(memory
mapped)
External I/O
(with
acknowledge)
Bus state
controller
Legend
DMAOR: DMAC operation register
SARn: DMAC source address register
DARn: DMAC destination address register
DMATCRn: DMAC transfer count register
CHCRn: DMAC channel control register
DEIn: DMA transfer-end interrupt request to
CPU
n = 0 to 3
Figure 12.1 Block Diagram of DMAC
Rev. 5.0, 09/03, page 371 of 806