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SH7729R Datasheet, PDF (115/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series | |||
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Branch Instructions
Table 2.24 Branch Instructions
Instruction
Operation
Code
BF
label
If T = 0, disp à 2 + PC â PC; 10001011dddddddd
if T = 1, nop (where label is
disp + PC)
BF/S label
Delayed branch, if T = 0,
disp à 2 + PC â PC;
if T = 1, nop
10001111dddddddd
BT
label
Delayed branch, if T = 1,
disp à 2 + PC â PC;
if T = 0, nop
10001001dddddddd
BT/S label
If T = 1, disp à 2 + PC â PC;
if T = 0, nop
10001101dddddddd
BRA label
Delayed branch,
disp à 2 + PC â PC
1010dddddddddddd
BRAF Rm
Delayed branch,
Rm + PC â PC
0000mmmm00100011
BSR label
Delayed branch, PC â PR,
disp à 2 + PC â PC
1011dddddddddddd
BSRF Rm
Delayed branch, PC â PR,
Rm + PC â PC
0000mmmm00000011
JMP @Rm
Delayed branch, Rm â PC
0100mmmm00101011
JSR @Rm
Delayed branch, PC â PR,
Rm â PC
0100mmmm00001011
RTS
Delayed branch, PR â PC
0000000000001011
Note: * One state when the branch is not executed.
Privileged
Mode
Cycles T Bit
â
3/1*
â
â
2/1*
â
â
3/1*
â
â
2/1*
â
â
2
â
â
2
â
â
2
â
â
2
â
â
2
â
â
2
â
â
2
â
Rev. 5.0, 09/03, page 69 of 806
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