SH7729R Datasheet, PDF (635/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• Serial data reception
Figures 17.9 and 17.10 show a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
1. Receive error handling and break detection: Read the DR, ER, and BRK flags in SCSSR to
identify any error, perform the appropriate error handling, then clear the DR, ER, and BRK
flags to 0. In the case of a framing error, a break can also be detected by reading the value of
the RxD pin.
2. SCIF status check and receive data read: Read the serial status register (SCSSR) and check that
RDF = 1, then read the receive data in the receive FIFO data register (SCFRDR), read 1 from
the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can
be identified by an RXI interrupt.
3. Serial reception continuation procedure: To continue serial reception, read at least the receive
trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear
the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by
reading the lower bits of SCFDR.
Rev. 5.0, 09/03, page 589 of 806