SH7729R Datasheet, PDF (727/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

22.2 Register Descriptions
22.2.1 D/A Data Registers 0 and 1 (DADR0/1)
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the
data to be converted. When analog output is enabled, the D/A data register values are constantly
converted and output at the analog output pins.
The D/A data registers are initialized to H'00 by a reset.
22.2.2 D/A Control Register (DACR)
Bit:
7
6
5
4
3
2
1
0
DAOE1 DAOE0 DAE
—
—
—
—
—
Initial value:
0
0
0
1
1
1
1
1
R/W: R/W R/W R/W
R
R
R
R
R
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter.
DACR is initialized to H'1F by a reset.
Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output.
Bit 7: DAOE1
0
1
Description
DA1 analog output is disabled
Channel-1 D/A conversion and DA1 analog output are enabled
(Initial value)
Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output.
Bit 6: DAOE0
0
1
Description
DA0 analog output is disabled
Channel-0 D/A conversion and DA0 analog output are enabled
(Initial value)
Rev. 5.0, 09/03, page 681 of 806