SH7729R Datasheet, PDF (573/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Start of transmission/reception
Read TDRE bit in SCSSR
(1)
No
TDRE = 1?
Yes
Write transmit data to SCTDR
and clear TDRE bit in SCSSR to 0
Read ORER bit in SCSSR
ORER = 1?
No
Yes
(2)
Error processing
Read RDRF bit in SCSSR
(3)
No
RDRF = 1?
Yes
Read receive data from SCRDR ₍₄₎
and clear RDRF bit in SCSSR to 0
No
All data
transmitted/received?
Yes
Clear TE and RE bits
in SCSCR to 0
End of transmission/reception
Notes: 1. Numbers in parentheses refer to steps in the preceding procedure description.
2. In switching from transmitting or receiving to simultaneous transmitting
and receiving, clear both TE and RE to 0, then set both TE and RE to 1 simultaneously.
Figure 15.23 Sample Flowchart for Transmitting/Receiving Serial Data
Rev. 5.0, 09/03, page 527 of 806