SH7729R Datasheet, PDF (246/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 3 and 2—Read/Write Select A (RWA1, RWA0): Select a read cycle or write cycle as the
bus cycle of the channel A break condition.
Bit 3: RWA1
0
1
Bit 2: RWA0
0
1
0
1
Description
Condition comparison is not performed
Break condition is read cycle
Break condition is write cycle
Break condition is read cycle or write cycle
(Initial value)
Bits 1 and 0—Operand Size Select A (SZA1, SZA0): Select the operand size of the bus cycle
for the channel A break condition.
Bit 1: SZA1
0
1
Bit 0: SZA0
0
1
0
1
Description
Break condition does not include operand size
Break condition is byte access
Break condition is word access
Break condition is longword access
(Initial value)
Rev. 5.0, 09/03, page 200 of 806