SH7729R Datasheet, PDF (260/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

8.2.13 Break ASID Register A (BASRA)
Bit: 7
BASA7
Initial value: *
R/W: R/W
Note: * Undefined
6
BASA6
*
R/W
5
BASA5
*
R/W
4
BASA4
*
R/W
3
BASA3
*
R/W
2
BASA2
*
R/W
1
BASA1
*
R/W
0
BASA0
*
R/W
Break ASID register A (BASRA) is an 8-bit readable/writable register that specifies the ASID that
serves as the break condition for channel A. It is not initialized by a reset. It is located in CCN.
Bits 7 to 0—Break ASID A7 to 0 (BASA7 to BASA0): These bits store the ASID (bits 7 to 0)
that is the channel A break condition.
8.2.14 Break ASID Register B (BASRB)
Bit: 7
BASB7
Initial value: *
R/W: R/W
Note: * Undefined
6
BASB6
*
R/W
5
BASB5
*
R/W
4
BASB4
*
R/W
3
BASB3
*
R/W
2
BASB2
*
R/W
1
BASB1
*
R/W
0
BASB0
*
R/W
Break ASID register B (BASRB) is an 8-bit readable/writable register that specifies the ASID that
serves as the break condition for channel B. It is not initialized by a reset. It is located in CCN.
Bits 7 to 0—Break ASID A7 to 0 (BASB7 to BASB0): These bits store the ASID (bits 7 to 0)
that is the channel B break condition.
Rev. 5.0, 09/03, page 214 of 806