SH7729R Datasheet, PDF (257/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

When the execution-times break condition of channel B is enabled, this register specifies the
number of execution times to make the break. The maximum number is 2¹² – 1 times. BETR is
initialized to H'0000 by a power-on reset. When a break condition is satisfied, the BETR value is
decremented by 1. A break is issued when the break condition is satisfied after the BETR value
reaches H'0001. Bits 15–12 are always read as 0, and 0 should always be written to these bits.
8.2.11 Branch Source Register (BRSR)
Bit: 31
SVF
Initial value: 0
R/W: R
30
PID2
*
R
29
PID1
*
R
28
PID0
*
R
27
BSA27
*
R
26
BSA26
*
R
25
BSA25
*
R
24
BSA24
*
R
Bit:
Initial value:
R/W:
23
BSA23
*
R
22
BSA22
*
R
21
BSA21
*
R
20
BSA20
*
R
19
BSA19
*
R
18
BSA18
*
R
17
BSA17
*
R
16
BSA16
*
R
Bit:
Initial value:
R/W:
15
BSA15
*
R
14
BSA14
*
R
13
BSA13
*
R
12
BSA12
*
R
11
BSA11
*
R
10
BSA10
*
R
9
BSA9
*
R
8
BSA8
*
R
Bit:
Initial value:
R/W:
Note: * Undefined
7
BSA7
*
R
6
BSA6
*
R
5
BSA5
*
R
4
BSA4
*
R
3
BSA3
*
R
2
BSA2
*
R
1
BSA1
*
R
0
BSA0
*
R
BRSR is a 32-bit read-only register that stores the last fetched address before a branch and the
pointer (3 bits) which indicates the number of cycles from fetch to execution for the last executed
instruction. BRSR has a flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0
when BRSR is read, and also is initialized by a power-on reset or manual reset. Other bits are not
initialized by a reset. Four BRSR registers have a queue structure and the stored register is shifted
every branch.
Rev. 5.0, 09/03, page 211 of 806